Identification of spatial defects in semiconductor manufacturing

In this article, we investigate the occurrence of defects in integrated circuit fabrication and show how spatial analysis can be effective in grasping and representing spatial regularities in defect patterns on the silicon supports, called wafers, used to produce microchips. Defects occurring on the wafer surface are the main cause of yield loss in the semiconductor industry; hence, to promptly detect an excess of defects and identify their spatial structure is crucial to the entire fabrication process. To address this hard-to-solve problem, this article proposes a concatenation of different methods, namely, a control chart, a clustering algorithm, and a graphical tool. First, a control chart based on the p-value of an appropriate test recognizes spatially structured defects on the wafer area. Then a clustering procedure grounded on the minimum spanning tree algorithm is adopted to identify those regions more prone to defect occurrences. Finally, alpha-shapes are employed to display their shape effectively. The suggested procedure proves to be extremely fast and effective, allowing its implementation in-line during the fabrication process. This provides a great advantage in modern microelectronics where items tend to be highly specialized and often produced in small lots. In particular, due to the Monte Carlo nature of the procedure, the control chart proposed hereafter does not require gold standard data to be set. This is particularly advantageous for small lot production, which is typically limited in time and does not permit to collect long time series of the charting statistics.